Abracon | Why does Reference Clock Jitter Matter?

Why does Reference Clock Jitter Matter?

Since the inception of the serial data transceiver, reference clock jitter has been a strong consideration when designing communications links. Is it a surprise that low clock jitter has remained significant? Why does clock jitter matter?

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Since the inception of the serial data transceiver, reference clock jitter has been a strong consideration when designing communications links. Is it a surprise that low clock jitter has remained significant? Why does clock jitter matter?

Many hardware engineers wonder whether there is a way to design around reference clock jitter. The importance of reference clock jitter comes down to two basic concepts—clock multiplication and transmitter PLL loop bandwidth.

In order to serialize data from a parallel path that is M bits wide into a single serial bit stream, the data must be clocked M times faster. This requires clock multiplication typically using a phase locked loop (PLL). The PLL acts like a low pass filter with respect to source phase noise. It attenuates source phase noise above the bandwidth knee and passes phase noise below its bandwidth with a 20log(M) gain. Clock phase noise below the -3dB bandwidth is effectively gained up. Clock phase noise above the -3dB bandwidth point is attenuated with a roll-off.

This fundamental relationship means that reference clock noise can never be eliminated from the transmitter output. Any serial transceiver using a PLL to generate M times higher bit rate has this property. Since there is phase noise gain below the -3dB knee of the transmitter, clock phase noise is actually amplified by a factor directly related to the ratio of the output bit rate and the reference clock frequency—20log(M) or 20log(output bit rate/clock frequency). This relationship assumes that you are comparing a clock of line rate frequency which is actually 2X the frequency of a 101010 data pattern. There is a built in factor of 2 shift when measuring the phase noise of the data compared to the line clock. Ignoring that detail for the purpose of this simplified analysis, the greater the multiple between your reference clock and the bit rate, the higher your in-band phase noise multiplication.

In today’s designs where bit rates have doubled from a few years ago, this means that your reference clock phase noise, and ultimately jitter, continues to be important. Multiplying up to line rates of 32Gbps or 56Gbps means you are gaining in-band phase clock phase noise by a factor greater than 40dB, two orders of magnitude. A reference clock without sufficiently low phase noise below the transceiver’s -3dB bandwidth will impact the output noise and could degrade bit error rate. Since bit rates are increasing, the in-band gain factor continues to increase.

Today’s trend compounds the effect because higher speed transceivers tend to also have higher -3dB PLL bandwidth. The part of the phase noise considered in-band tends to increase by a wide factor. Where it was common to design transceivers with transmitter -3dB bandwidths around 10MHz to 20MHz, this may no longer be possible. In many applications the knee has stretched beyond 80MHz. This is why some high speed IC manufacturers require reference clock jitter to be integrated up to 80MHz. They may develop a custom integration band to characterize jitter. Another common practice is to use the typical 12kHz to 20MHz band as a standard figure of merit. If the overall phase jitter is low enough throughout that band, it is assumed that it is low enough when extended to a wider range of 80MHz or 40MHz. In practice, jitter should be measured up to the full integration range of the transmitter PLL.

Reference clock jitter has become a greater design challenge. When combined, higher clock rate multiplication and wider overall transmitter PLL bandwidths compound the overall effect of clock noise on transceiver output jitter. Although the actual effect on BER can only be determined when considering the loop dynamics of the receiving side, excess phase noise will definitely show up on the output. As transceiver line rates increase reference clocks must exhibit considerably lower noise.

About Abracon, LLC

Founded in 1992, and headquartered in Spicewood, Texas, Abracon is a leading global manufacturer of passive and electromechanical timing, synchronization, power, connectivity and RF solutions. Abracon offers a wide selection of quartz timing crystals and oscillators, MEMS oscillators, real time clocks (RTC), Bluetooth modules, ceramic resonators, SAW filters and resonators, power and RF inductors, transformers, circuit protection components and RF antennas and wireless charging coils. The company is ISO9001-2015 certified with design & application engineering resources in Texas and sales offices in Texas, California, China, Taiwan, Singapore, Scotland, Israel, Hungary, UK, and Germany. Abracon’s products are offered through its global distribution network. For more information about Abracon, visit www.abracon.com.

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